diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 8eb5e30..f464379 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -28,7 +28,6 @@
 	imply CMD_PING
 	imply CLK_SIFIVE
 	imply CLK_SIFIVE_FU540_PRCI
-	imply CLK_SIFIVE_GEMGXL_MGMT
 	imply DOS_PARTITION
 	imply EFI_PARTITION
 	imply IP_DYN
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index d90be19..c4d0a1f 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -14,10 +14,3 @@
 	  Supports the Power Reset Clock interface (PRCI) IP block found in
 	  FU540 SoCs.  If this kernel is meant to run on a SiFive FU540 SoC,
 	  enable this driver.
-
-config CLK_SIFIVE_GEMGXL_MGMT
-	bool "GEMGXL management for SiFive FU540 SoCs"
-	depends on CLK_SIFIVE
-	help
-	  Supports the GEMGXL management IP block found in FU540 SoCs to
-	  control GEM TX clock operation mode for 10/100/1000 Mbps.
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index 0813360..b224279 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,5 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)		+= fu540-prci.o
-
-obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT)		+= gemgxl-mgmt.o
diff --git a/drivers/clk/sifive/gemgxl-mgmt.c b/drivers/clk/sifive/gemgxl-mgmt.c
deleted file mode 100644
index eb37416..0000000
--- a/drivers/clk/sifive/gemgxl-mgmt.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <asm/io.h>
-
-struct gemgxl_mgmt_regs {
-	__u32 tx_clk_sel;
-};
-
-struct gemgxl_mgmt_platdata {
-	struct gemgxl_mgmt_regs *regs;
-};
-
-static int gemgxl_mgmt_ofdata_to_platdata(struct udevice *dev)
-{
-	struct gemgxl_mgmt_platdata *plat = dev_get_platdata(dev);
-
-	plat->regs = (struct gemgxl_mgmt_regs *)dev_read_addr(dev);
-
-	return 0;
-}
-
-static ulong gemgxl_mgmt_set_rate(struct clk *clk, ulong rate)
-{
-	struct gemgxl_mgmt_platdata *plat = dev_get_platdata(clk->dev);
-
-	/*
-	 * GEMGXL TX clock operation mode:
-	 *
-	 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
-	 *     and output clock on GMII output signal GTX_CLK
-	 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
-	 */
-	writel(rate != 125000000, &plat->regs->tx_clk_sel);
-
-	return 0;
-}
-
-const struct clk_ops gemgxl_mgmt_ops = {
-	.set_rate = gemgxl_mgmt_set_rate,
-};
-
-static const struct udevice_id gemgxl_mgmt_match[] = {
-	{ .compatible = "sifive,cadencegemgxlmgmt0", },
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(sifive_gemgxl_mgmt) = {
-	.name = "sifive-gemgxl-mgmt",
-	.id = UCLASS_CLK,
-	.of_match = gemgxl_mgmt_match,
-	.ofdata_to_platdata = gemgxl_mgmt_ofdata_to_platdata,
-	.platdata_auto_alloc_size = sizeof(struct gemgxl_mgmt_platdata),
-	.ops = &gemgxl_mgmt_ops,
-};